How Intel shrank processors to 45nm without taking a leak

Pictured left is a die shot of one of Intel's new 45nm Penryn processors, which the company claims represent the biggest breakthough since the sixties. Its development forced Intel to address one of the biggest problems of miniaturisation: leakage current.

A standard transistor of the type used in processors consists of source and drain electrodes sitting in a silicon substrate with a tiny gap between them. Above this gap is a thin layer of insulator, or dielectric; and sitting on that is the gate electrode (click image at right for pop-up diagram). Toggling the voltage at the gate toggles the charge distribution across the gap, and thus its ability to pass current.

This solid-state switch is never quite perfect because there are tiny current flows even in the off state. Most important is the "leakage" across the insulating layer under the gate. This layer is made of silicon dioxide (SiO2) in current designs and when it becomes only a few atoms thick, as it does as processor transistors get smaller, leakage becomes prohibitively high.

So why not have thicker insulation? The problem is that the thinner the layer, the higher is the capacitance of the structure - the amount of charge it can hold. The higher the capacitance, the better the current flow in the on state, and the faster the switching. In other words if you thicken the insulation to reduce leakage, you slow the transistor down.

What Intel has done is to replace the SiO2 with a 'high K dielectric', based on the element Hafnium, which allows a thicker (and thus less leaky) layer of insulation without reducing the capacitance.

Intel has also replaced the usual silicon gate with what it vaguely refers to as a mix of metals. Kaizad Mistry, product manager for Intel's 45nm logic technology development, said Intel was keeping this secret as the precise proportions of these and hafnium are critical.

The overall effect is to boost current flow in the on state, providing fast switching, and cutting leakage in the off state.

Intel claims that relative to 65nm technology the Penryn chips will pack twice as many transistors in a given area, with a 30 percent reduction in switching power, 20 percent faster switching, and a tenfold reduction in leakage across the gate dielectric. It also claims a fivefold reduction in current leaking between the source and drain.

reposted from: http://labs.pcw.co.uk/2007/01/how_intel_shran.html

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